EPF10K200SRC240-3 vs EPF10K200SRC240-3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K200SRC240-3 sa pamamagitan ng Intel at EPF10K200SRC240-3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K200SRC240-3 | EPF10K200SRC240-3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | FLEX 10KE | FLEX 10KE |
| Series | FLEX-10KS | — |
| Logic Elements / Cells | 9984 | — |
| Total System Gates | 200,000 | — |
| Total RAM Bits | 98,304 | — |
| Number of LABs/CLBs | 1248 | — |
| Number of I/Os | 470 | — |
| Number of DLLs | 4 | — |
| Packhaging | 240-BFQFP Exposed Pad (RQFP-240) | 240-pin RQFP (Power QFP) with exposed pad, 34.6 x 34.6 mm, 0.5 mm pitch |
| Package Dimensions | 34.60 x 34.6 mm, 0.5 mm pitch | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS SRAM |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | MultiVolt (2.5 V / 3.3 V / 5.0 V tolerant) | — |
| Maximum Internal Frequency | 166.67 MHz | — |
| Propagation Delay | 0.4 ns | — |
| Temperature na Operasyon | 0 C to 70 C (Commercial) | 0 °C to +70 °C (Commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Typical System Gates | — | 200,000 |
| Logic Elements (LEs) | — | 9,984 |
| Maximum Logic Elements | — | 9,984 |
| Embedded Array Blocks (EABs) | — | 24 |
| Maximum User RAM Bits | — | 98,304 |
| Logic Array Blocks (LABs) | — | 1,248 |
| User I/Os | — | 470 (effective); 182 user pins per RQFP-240 with the rest assigned to dedicated functions |
| Propagation Delay (tPD) | — | 0.40 ns |
| Internal Operating Frequency | — | 166.67 MHz |
| Core Supply Voltage | — | 2.5 V |
| MultiVolt I/O Support | — | 2.5 V and 3.3 V interfaces |
| JTAG Support | — | IEEE Std 1149.1 Boundary-Scan (contributes up to 31,250 gates of test logic) |
| Configuration Method | — | SRAM-based; requires external configuration device (e.g., EPC2) for power-up loading |
| Speed Grade | — | -3 (commercial) |