EPF10K250EFI672-3 vs EPF10K250EFC672-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K250EFI672-3 sa pamamagitan ng Intel at EPF10K250EFC672-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPF10K250EFI672-3 EPF10K250EFC672-2
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family FLEX 10KE FLEX 10KE
Typical Gates 250,000 250,000
Logic Elements [DATA_NEEDED: exact LE count] 12,480
User I/O Pins 470 —
Embedded Array Blocks (EABs) 12 20
EAB Dual-Port Width Up to 16-bit —
Maximum EAB Memory [DATA_NEEDED: bits per EAB] —
Propagation Delay (tpd) 0.4 ns (typical, -3 speed grade) —
Core Supply Voltage 2.5 V 2.3 V (typical 2.5 V)
I/O Supply Voltage 2.5 V / 3.3 V (multiVolt I/O) —
Packhaging 672-ball FineLine BGA, 1.27 mm pitch 672-BGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch
Process Technology CMOS, SRAM-based configuration —
Configuration Interface JTAG / ByteBlaster (EPC2/EPC8 PROM) —
Temperature na Operasyon 0 °C to 70 °C (commercial) 0 C to +70 C (Commercial)
Design Entry EDIF 2 0 0 / 3 0 0, LPM, VHDL, Verilog —
Tindminan RoHS Unknown (legacy Altera non-RoHS device) Non-RoHS Compliant (per Fly-Wing listing)
Maximum User RAM Bits — 40,960
User I/Os — 470
Bilang ng Pin — 672
Propagation Delay — 0.4 ns
I/O Standard Support — 1.8 V, 2.5 V, 3.3 V (multi-volt I/O)
Logic Family — CMOS, SRAM-based
Configuration — SRAM, in-system programmable (ISP) via JTAG
Boundary Scan — IEEE 1149.1 (JTAG) compliant
Uri ng Pagpapasok — Surface Mount

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita