EPM1270F256I5 vs EPM1270F256 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM1270F256I5 sa pamamagitan ng Altera at EPM1270F256 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM1270F256I5 | EPM1270F256 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Presyo ng Yunit (USD) | — | $10.85 |
| Device Family | MAX II | — |
| Series | EPM1270 | — |
| Macrocell Count | 980 | — |
| Logic Elements | 1270 | 1270 |
| User I/O Pins | 212 (max) | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Packhaging | 256-ball FBGA (FineLine BGA) | 256-Pin FineLine BGA |
| Pin/Package Count | 256 | — |
| Process Technology | 0.18 µm | 0.18 µm |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V | — |
| Maximum Internal Frequency | 201.1 MHz | — |
| Pin-to-Pin Delay (tPD) | 6.2 ns | — |
| Temperature na Operasyon | -40 °C to +100 °C (industrial, "I") | -40C to +100C (industrial, I5N suffix) |
| Speed Grade | 5 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Family | — | MAX II |
| Macro Cells (Typical) | — | 980 |
| User I/O (Max) | — | 212 |
| Supply Voltage (Core) | — | 2.5 V / 3.3 V (on-chip regulator) |
| I/O Voltages Supported | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Maximum Frequency | — | 201.1 MHz |
| Configuration Memory | — | Non-volatile flash (instant-on) |
| Vertical Migration | — | Pin-compatible with EPM570F256 and EPM2210F256 |