EPM240GM100C5N vs EPM240F100C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240GM100C5N sa pamamagitan ng Altera at EPM240F100C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240GM100C5N - 192-Cell MAX II G CPLD, 4.7ns, 100-MBGA | Intel / Altera
EPM240GM100C5N ✓ Nakahanda
Pagsanggunian na paghahambing
| Parametro | EPM240GM100C5N | EPM240F100C5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II G | — |
| Logic Elements | 240 (192 macrocells) | — |
| User I/Os | 80 | — |
| Pin-to-Pin Delay (tPD) | 4.7 ns | — |
| Packhaging | 100-MBGA (Micro FineLine BGA), 6 x 6 mm | 100-ball FineLine BGA (FBGA-100) |
| Ball Pitch | 0.5 mm | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multiVolt) | — |
| Programming Interface | JTAG (IEEE 1149.1) - ISP | JTAG / ByteBlasterMV |
| Configuration Memory | Non-volatile Flash | Non-volatile flash (instant-on) |
| Temperature na Operasyon | -40 C to +125 C | — |
| Lead Free / RoHS | Yes / Compliant | — |
| Level ng MSL | 3 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Process Technology | CMOS, Flash-based | — |
| Device Family | — | MAX II |
| Logic Elements (LEs) | — | 240 |
| Macrocells | — | 192 |
| User I/O Pins (maximum) | — | 80 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.7 ns |
| Maximum Operating Frequency | — | [DATA_NEEDED: fmax per datasheet] |
| Global Clock Networks | — | [DATA_NEEDED: count] |
| Hanay ng Temperature na Operasyon | — | 0C to +85C (commercial) |
| Supply Voltage Core (VCCINT) | — | 3.3 V |
| I/O Bank Voltage (VCCIO) | — | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Tindminan RoHS | — | Compliant |