EPM240M100I5N vs EPM240M100C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240M100I5N sa pamamagitan ng Altera at EPM240M100C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM240M100C4N - 192 Macrocell MAX II CPLD, 100-MBGA | Intel / Altera
EPM240M100C4N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240M100I5N | EPM240M100C4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | MAX II |
| Family | MAX II CPLD | — |
| Macro Cells | 192 | 192 |
| Logic Elements | 240 | — |
| Maximum Internal Frequency | 201.1 MHz | — |
| Propagation Delay (tPD) | 4.7 ns | — |
| On-die Non-volatile Memory | 8 Kbits | — |
| Process Technology | 0.18 µm, 6-layer metal flash | — |
| Core Voltage | 2.5 V / 3.3 V | — |
| I/O Bank Voltages | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User I/O Pins | [DATA_NEEDED: user IO count for MBGA package] | — |
| Packhaging | 100-MBGA (Micro FineLine BGA) | 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch |
| Temperature na Operasyon | -40 °C to +100 °C (industrial) | -40 C to +125 C (industrial) |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Tindminan RoHS | Compliant | Lead Free (per DigiChip spec sheet) |
| Lead-Free | Yes | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Device Family | — | EPM240 |
| User I/Os | — | 80 |
| Propagation Delay (tPD) Max | — | 4.7 ns |
| Internal Operating Frequency | — | 247.5 MHz |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| User Flash Memory | — | 8 Kbit |
| Programmability | — | In-System Programmable via JTAG (IEEE 1149.1) |
| Configuration Memory | — | Non-volatile on-chip flash (instant-on) |
| Logic Family | — | CMOS |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells per LAB) |
| MultiTrack Interconnect | — | Yes |
| Hot Socketing | — | Yes |