EPM240M100I5N vs EPM240M100C4N 比較

詳細並排比較 EPM240M100I5N 由 Altera 與 EPM240M100C4N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM240M100I5N EPM240M100I5N - MAX II CPLD 192 MC 100MBGA | Altera

EPM240M100I5N - MAX II CPLD 192 MC 100MBGA | Altera

EPM240M100I5N ✓ 啟用中

規格比較

參數 EPM240M100I5N EPM240M100C4N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Series MAX II MAX II
Family MAX II CPLD —
Macro Cells 192 192
Logic Elements 240 —
Maximum Internal Frequency 201.1 MHz —
Propagation Delay (tPD) 4.7 ns —
On-die Non-volatile Memory 8 Kbits —
Process Technology 0.18 µm, 6-layer metal flash —
Core Voltage 2.5 V / 3.3 V —
I/O Bank Voltages 1.5 V / 1.8 V / 2.5 V / 3.3 V —
User I/O Pins [DATA_NEEDED: user IO count for MBGA package] —
封裝 100-MBGA (Micro FineLine BGA) 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch
工作溫度 -40 °C to +100 °C (industrial) -40 C to +125 C (industrial)
Programming Interface JTAG (IEEE 1149.1) —
RoHS 狀態 Compliant Lead Free (per DigiChip spec sheet)
Lead-Free Yes —
安裝類型 Surface Mount (BGA) Surface Mount (BGA)
Device Family — EPM240
User I/Os — 80
Propagation Delay (tPD) Max — 4.7 ns
Internal Operating Frequency — 247.5 MHz
Supply Voltage - Core — 2.5 V / 3.3 V
I/O Standards Supported — 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL
User Flash Memory — 8 Kbit
Programmability — In-System Programmable via JTAG (IEEE 1149.1)
Configuration Memory — Non-volatile on-chip flash (instant-on)
Logic Family — CMOS
Logic Array Blocks (LABs) — 4 (16 macrocells per LAB)
MultiTrack Interconnect — Yes
Hot Socketing — Yes

資料表與資源

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