EPM240T100C4 vs EPM240T100A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240T100C4 sa pamamagitan ng Intel at EPM240T100A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240T100A5N - 192-Macrocell MAX II CPLD, 100-TQFP | Intel / Altera
EPM240T100A5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240T100C4 | EPM240T100A5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | — |
| Programmable Type | In System Programmable | — |
| Number of Macrocells | 192 | — |
| Number of Logic Elements/Blocks | 240 | — |
| Number of User I/O | 80 | — |
| Maximum Propagation Delay (tPD) | 4.7 ns | — |
| Internal Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 µm CMOS, non-volatile Flash | 0.18 µm |
| User Flash Memory | 8 Kbits (typical) | — |
| Packhaging / Kaso | 100-pin TQFP | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 °C to +85 °C (TJ, commercial) | 0C to +85C (commercial, "A5N" suffix) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP | JTAG (IEEE 1149.1) / ISP |
| Supplier Device Package | 100-TQFP (16 × 16 mm, 0.5 mm pitch) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (Pb-free) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX II |
| Macro Cells | — | 192 |
| Logic Elements (LE) | — | 240 |
| User I/O Count | — | 80 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Volte ng Pagbibigay | — | 2.5 V / 3.3 V |
| I/O Bank Count | — | 4 (multi-voltage) |
| Configuration Memory | — | On-chip Flash (instant-on) |
| Packhaging | — | 100-pin TQFP (14 x 14 x 1.0 mm) |