EPM240T100C4N vs EPM240M100C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240T100C4N sa pamamagitan ng Altera at EPM240M100C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM240M100C4N - 192 Macrocell MAX II CPLD, 100-MBGA | Intel / Altera
EPM240M100C4N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240T100C4N | EPM240M100C4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | — |
| Device | EPM240 | — |
| Macro Cells | 192 | 192 |
| Logic Elements | 240 | — |
| Propagation Delay (tPD) | 4.7 ns (max) | — |
| Maximum Frequency | 247.5 MHz | — |
| User I/O | 80 | — |
| Supply Voltage - Internal | 2.5 V / 3.3 V | — |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm | — |
| Programmable Type | In-System Programmable (Flash) | — |
| Packhaging / Kaso | 100-TQFP | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | 0 °C to +85 °C (commercial, 'C' suffix) | -40 C to +125 C (industrial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | Compliant (lead-free, 'N' suffix) | Lead Free (per DigiChip spec sheet) |
| Series | — | MAX II |
| Device Family | — | EPM240 |
| User I/Os | — | 80 |
| Propagation Delay (tPD) Max | — | 4.7 ns |
| Internal Operating Frequency | — | 247.5 MHz |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| User Flash Memory | — | 8 Kbit |
| Programmability | — | In-System Programmable via JTAG (IEEE 1149.1) |
| Configuration Memory | — | Non-volatile on-chip flash (instant-on) |
| Logic Family | — | CMOS |
| Packhaging | — | 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells per LAB) |
| MultiTrack Interconnect | — | Yes |
| Hot Socketing | — | Yes |