EPM240ZM100C7N vs EPM240ZM68C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240ZM100C7N sa pamamagitan ng Altera at EPM240ZM68C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240ZM100C7N - MAX II Z CPLD 192MC 7.5ns 100-MBGA | Altera/Intel
EPM240ZM100C7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240ZM100C7N | EPM240ZM68C6N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II Z | MAX II Z (CPLD) |
| Series | MAX II | — |
| Logic Elements | 240 | — |
| Macrocells | 192 | 192 |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns | — |
| User I/Os | 80 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Core Supply Voltage (VCCINT) | 1.8 V | 1.8 V |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (banked) |
| Packhaging | 100-MBGA (Micro FineLine BGA), 6 x 6 mm | 68-ball Micro FBGA (MBGA-68) |
| Configuration Memory | On-chip non-volatile flash | On-chip flash (non-volatile, instant-on) |
| Process Technology | 0.18 µm 6-layer-metal flash | 0.18 µm |
| JTAG Support | IEEE 1149.1 (programming + boundary-scan) | — |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Lead-Free / RoHS | Compliant per datasheet | — |
| Logic Elements (LE) | — | 240 |
| Maximum Propagation Delay (tPD) | — | 7.5 ns |
| Internal Performance (fMAX) | — | 184.1 MHz |
| User I/O Count | — | 80 |
| Number of I/O Banks | — | 4 |
| Programming Interface | — | JTAG (IEEE 1149.1 / IEEE 1532) |
| Hanay ng Temperature na Operasyon | — | -40°C to +85°C (commercial, 'C' suffix) |
| Tindminan RoHS | — | Compliant |
| Lead-Free Finish | — | Yes |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |