EPM3032ALC44-4 vs EPM3032ALC44-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3032ALC44-4 sa pamamagitan ng Altera at EPM3032ALC44-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3032ALC44-4 EPM3032ALC44-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 3000A MAX 3000A
Macrocells 32 32
Logic Array Blocks (LABs) 2 2
User I/O Pins 34 34
Pin-to-Pin Delay (tPD) 4.5 ns —
Maximum Counter Frequency 227.3 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible) —
Usable Gates 600 to 10,000 (MAX 3000A family range) —
Packhaging 44-pin PLCC (J-Lead) 44-pin PLCC (J-Lead, surface mount)
Temperature na Operasyon 0°C to +70°C (Commercial) [DATA_NEEDED: industrial/commercial range]
Technology CMOS EEPROM-based CMOS EEPROM-based
In-System Programmability (ISP) Yes, IEEE Std. 1532 compliant —
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) —
Programming Interface JTAG (ByteBlaster / MasterBlaster) —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: compliant or non-compliant]
Uri ng Pagpapasok Surface Mount (PLCC J-Lead) Surface Mount
Product Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 600 gates
Propagation Delay (tPD) — 10 ns
Internal fMAX — 103.1 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O)
In-System Programmability — Yes, via IEEE 1149.1 JTAG
ISP Standard Compliance — IEEE Std. 1532
Boundary-Scan Test (BST) — Yes, IEEE 1149.1 compliant

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