EPM3032ALC44-4 vs EPM3032ALC44-4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3032ALC44-4 sa pamamagitan ng Altera at EPM3032ALC44-4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3032ALC44-4 | EPM3032ALC44-4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 34 | 34 |
| Pin-to-Pin Delay (tPD) | 4.5 ns | 4.5 ns |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Usable Gates | 600 to 10,000 (MAX 3000A family range) | 600 |
| Packhaging | 44-pin PLCC (J-Lead) | 44-pin PLCC (J-Lead) |
| Temperature na Operasyon | 0°C to +70°C (Commercial) | [DATA_NEEDED: industrial/commercial grade] |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability (ISP) | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| Programming Interface | JTAG (ByteBlaster / MasterBlaster) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: from datasheet] |
| Uri ng Pagpapasok | Surface Mount (PLCC J-Lead) | Surface Mount |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum Counter Frequency (fCNT) | — | 227.3 MHz |
| Programmability | — | EEPROM (non-volatile), IEEE 1149.1 JTAG ISP, IEEE 1532 compliant |