EPM3064ALI44-10N vs EPM3064ALC44-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ALI44-10N sa pamamagitan ng Altera at EPM3064ALC44-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ALI44-10N EPM3064ALC44-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Series MAX 3000A —
Programmable Type In System Programmable (ISP) —
Number of Macrocells 64 —
Number of I/O 34 —
Logic Gates 1250 gates —
Number of Logic Elements/Blocks 4 LABs —
Propagation Delay (tPD) 10 ns (speed grade -10) 10 ns
Counter Frequency up to 227.3 MHz —
Supply Voltage - Core 3.3 V —
I/O Logic Level Support 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Programming Interface IEEE Std. 1149.1 JTAG —
Temperature na Operasyon -40 C to +85 C (Industrial) [DATA_NEEDED: commercial / industrial grade]
Packhaging 44-pin PLCC (J-Lead) 44-pin PLCC (LC44)
Uri ng Pagpapasok Surface Mount (socketable PLCC) Surface Mount (PLCC socket compatible)
Lead Free / RoHS Status Lead Free, RoHS Compliant —
Hot-Socketing Support Yes —
Configuration Memory CMOS EEPROM (non-volatile) CMOS EEPROM
Product Family — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 64
Logic Array Blocks (LABs) — 4
User I/O Pins — 34
Usable Gates — 1,250
Maximum Counter Frequency — 227.3 MHz
Supply Voltage (VCCINT) — 3.0 V to 3.6 V
I/O Bank Voltage (VCCIO) — 3.0 V to 3.6 V (MultiVolt)
In-System Programmability — Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant)
Tindminan RoHS — Compliant
Open-Drain Output Option — Yes (per I/O pin)
Output Slew-Rate Control — Programmable

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