EPM3256AFC256-7 vs EPM3128AFC256-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256AFC256-7 sa pamamagitan ng Altera at EPM3128AFC256-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3256AFC256-7 | EPM3128AFC256-7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 256 | 128 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 10,000 | 2,500 |
| User I/Os | 161 | 98 |
| Pin-to-Pin Logic Delay | 4.5 ns (max) | — |
| Counter Frequency | 227.3 MHz (max) | — |
| Propagation Delay (tpd) | 10 ns | — |
| Core Voltage | 3.3 V | — |
| I/O Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) | — |
| Process Technology | CMOS EEPROM, 0.30 µm | — |
| In-System Programmability | IEEE Std. 1532-compliant 3.3-V ISP | — |
| Boundary-Scan Test | JTAG (IEEE 1149.1) | — |
| Packhaging | FBGA-256 (FineLine BGA), 256 balls | 256-BGA (FineLine, FBGA) |
| Temperature na Operasyon | 0 °C to 70 °C (Commercial) | 0 C to +70 C (commercial) |
| Speed Grade | -7 | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Architecture | — | CMOS EEPROM-based MAX |
| Propagation Delay (tPD) | — | 7.5 ns |
| Internal fMAX | — | 192.3 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 3.3 V or 2.5 V |
| Logic Family | — | CMOS |
| Programmability | — | In-system (ISP), IEEE Std. 1532, JTAG (IEEE Std. 1149.1) |
| Uri ng Pagpapasok | — | Surface Mount |