EPM3256AFI256-10 vs EPM3512AFC256C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256AFI256-10 sa pamamagitan ng Intel at EPM3512AFC256C sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3256AFI256-10 - 256-Macrocell CPLD, 10ns, FBGA-256 | Intel
EPM3256AFI256-10 ⚠ Huling PagbiliIntel
EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256C ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM3256AFI256-10 | EPM3512AFC256C |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | 512 |
| User I/Os | 161 | — |
| Logic Elements / LABs | 16 Logic Elements per LAB | — |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Voltage Support | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) | — |
| Programmability | In-System Programmable (ISP) via IEEE 1149.1 JTAG | — |
| Process Technology | CMOS EEPROM | — |
| Package Type | FBGA-256 (FineLine BGA) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | 0C to +70C (Commercial) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | -10 (10 ns pin-to-pin) | C (per datasheet ordering code) |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/Os | — | 208 |
| Dedicated Input Pins | — | 12 |
| Packhaging | — | 256-ball FineLine BGA (FC) |
| Configuration Technology | — | EEPROM (non-volatile, instant-on) |
| Core Voltage | — | 3.3 V |
| I/O Standards Supported | — | MultiVolt: 5.0 V, 3.3 V, 2.5 V |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| PCI Compliance | — | PCI SIG Local Bus Specification Revision 2.2 |
| Programming | — | In-system programmable via JTAG |