EPM3256AQC208-10 vs EPM3256AQC208-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256AQC208-10 sa pamamagitan ng Altera at EPM3256AQC208-7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3256AQC208-10 EPM3256AQC208-7N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Aktibo
Family MAX 3000A MAX 3000A
Logic Family CMOS (EEPROM-based) —
Macrocells 256 —
Usable Gates 5,000 —
User I/Os 161 161
Bilang ng Pins 208 —
Packhaging 208-BFQFP (PQFP, Gull Wing) 208-pin PQFP
Pin-to-Pin Propagation Delay 10 ns —
Counter Frequency (max) 227.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Tolerance MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant —
Programming Interface IEEE 1149.1 JTAG (ISP) —
Temperature na Operasyon 0 °C to +70 °C (Commercial) 0 C to +70 C (Commercial)
PCI-SIG Compliance Yes (speed grades -4, -5, -6, -7, -10) —
Global Clock Networks 4 (CLK, CLR, OE, GCLK) —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Type — CPLD - Complex Programmable Logic Device
Macro Cells — 256
Logic Gates (Usable) — 5,000
Propagation Delay (tPD) — 7.5 ns
Maximum Internal Frequency — 126.6 MHz
Supply Voltage VCCINT — 3.3 V
I/O Supply Voltage VCCIO — 3.3 V or 2.5 V (MultiVolt)
Programming Technology — EEPROM (non-volatile)
In-System Programmability — Yes, IEEE Std. 1532 compliant
JTAG Boundary Scan — Yes

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