EPM3256ATC144-7N vs EPM3512ATC144 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256ATC144-7N sa pamamagitan ng Altera at EPM3512ATC144 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3256ATC144-7N | EPM3512ATC144 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 256 | — |
| Logic Gates (usable) | 5,000 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 116 | — |
| Propagation Delay (tPD) | 7.5 ns | [DATA_NEEDED: tPD in ns] |
| Maximum Internal Frequency | 126.6 MHz | — |
| Supply Voltage (VCCIO) | 3.0 V to 3.6 V | — |
| Programmable Logic Technology | CMOS EEPROM-based | — |
| In-System Programmable (ISP) | Yes (3.3 V) | — |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Packhaging | 144-pin TQFP | TQFP-144 (20x20 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | Compliant | Compliant (lead-free suffix variants available) |
| Macrocells | — | 512 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Core Supply Voltage | — | 3.3 V |
| Programming Technology | — | EEPROM (in-system programmable) |
| JTAG Interface | — | IEEE Std. 1149.1 (4-pin) |
| Maximum Frequency | — | 116 MHz |
| Product Terms per Macrocell | — | 32 (expandable) |
| I/O Standards | — | LVTTL, LVCMOS, 2.5 V/3.3 V/5 V tolerant |
| Level ng MSL | — | 3 |