EPM3512AFC256-20 vs EPM3512AFC256-21 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-20 sa pamamagitan ng Altera at EPM3512AFC256-21 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 Obsolete
Pagsanggunian na paghahambing
| Parametro | EPM3512AFC256-20 | EPM3512AFC256-21 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 3000A | — |
| Macrocells | 512 | — |
| Typical Usable Gates | 10,000 | — |
| Speed Grade | -20 (20 ns tPD) | — |
| Packhaging | 256-ball FBGA (Fine-pitch BGA) | FBGA-256 (FineLine BGA) |
| Bilang ng Pin | 256 | — |
| Operating Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| I/O Standards | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| JTAG Support | Yes (boundary-scan + ISP) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Level ng MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Configuration Memory | Internal EEPROM | — |
| Device Family | — | MAX 3000A |
| Logic Elements / Macrocells | — | 512 macrocells |
| Usable Gates | — | 10,000 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Operating Frequency | — | 87 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) |
| Programmable Pins (max) | — | [DATA_NEEDED: maximum user I/O pin count] |
| Programming Interface | — | JTAG / IEEE Std. 1532 ISP |
| Uri ng Memory | — | Non-volatile EPROM/EEPROM cell array |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |