EPM3512AFC256-22 vs EPM3512AFC256-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-22 sa pamamagitan ng Intel at EPM3512AFC256-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-22 EPM3512AFC256-20
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 208 (typical for FC256 package) —
Speed Grade -22 (tPD ~22 ns) -20 (20 ns tPD)
Propagation Delay (tPD) 22 ns —
Supply Voltage VCCINT 3.3 V —
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
Configuration Memory On-chip EEPROM (non-volatile) Internal EEPROM
Packhaging FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) 256-ball FBGA (Fine-pitch BGA)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Typical Usable Gates — 10,000
Bilang ng Pin — 256
Operating Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Voltage (VCCIO) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
I/O Standards — LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type — EEPROM (non-volatile)
In-System Programmability — Yes (JTAG IEEE 1149.1)
JTAG Support — Yes (boundary-scan + ISP)
Level ng MSL — [DATA_NEEDED: MSL moisture sensitivity level]

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita