EPM3512AFC256-22 vs EPM3512AFC256-20 比較

詳細並排比較 EPM3512AFC256-22 由 Intel 與 EPM3512AFC256-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3512AFC256-22 EPM3512AFC256-20
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 208 (typical for FC256 package) —
Speed Grade -22 (tPD ~22 ns) -20 (20 ns tPD)
Propagation Delay (tPD) 22 ns —
Supply Voltage VCCINT 3.3 V —
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
Configuration Memory On-chip EEPROM (non-volatile) Internal EEPROM
封裝 FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) 256-ball FBGA (Fine-pitch BGA)
安裝類型 Surface Mount (BGA) Surface Mount
工作溫度 [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Typical Usable Gates — 10,000
腳位數 — 256
Operating Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Voltage (VCCIO) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
I/O Standards — LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type — EEPROM (non-volatile)
In-System Programmability — Yes (JTAG IEEE 1149.1)
JTAG Support — Yes (boundary-scan + ISP)
MSL 等級 — [DATA_NEEDED: MSL moisture sensitivity level]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價