EPM3512AFC256-7 vs EPM3512AFC256-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-7 sa pamamagitan ng Intel at EPM3512AFC256-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-7 EPM3512AFC256-10N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
User I/O Pins 212 208
Usable Gates 10,000 10000
Pin-to-Pin Logic Delay 7.5 ns —
Counter Frequency (max) 227.3 MHz —
Supply Voltage - Core (VCCINT) 3.0 V to 3.6 V (3.3 V typ.) —
I/O Voltage (VCCIO) 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Packhaging 256-ball FineLine BGA (FBGA-256) 256-ball FBGA (17 mm x 17 mm)
Programming EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] —
Uri ng Pagpapasok Surface Mount Surface Mount (BGA)
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Configuration Memory Non-volatile EEPROM —
Operating Frequency (fMAX) — [DATA_NEEDED: fMAX MHz]
Pin-to-Pin Delay (tPD) — 10 ns
Setup Time (tSU) — 4.5 ns
VCCINT (Core Supply) — 3.3 V
VCCIO (I/O Supply) — 3.3 V or 2.5 V
Technology — CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) — 0 C to +70 C
ISP Interface — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Level ng MSL — [DATA_NEEDED: MSL rating]

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