EPM3512AFC256C vs EPM3256AFC256-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256C sa pamamagitan ng Intel at EPM3256AFC256-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256C EPM3256AFC256-10N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 256
Logic Array Blocks (LABs) 16 —
Maximum User I/Os 208 —
Dedicated Input Pins 12 —
Packhaging 256-ball FineLine BGA (FC) 256-pin FineLine BGA
Temperature na Operasyon 0C to +70C (Commercial) 0 C to 70 C (commercial)
Speed Grade C (per datasheet ordering code) —
Configuration Technology EEPROM (non-volatile, instant-on) —
Core Voltage 3.3 V 3.3 V
I/O Standards Supported MultiVolt: 5.0 V, 3.3 V, 2.5 V —
JTAG Support IEEE 1149.1 Boundary Scan —
PCI Compliance PCI SIG Local Bus Specification Revision 2.2 PCI Local Bus Specification Rev 2.2 (at -10 grade)
Programming In-system programmable via JTAG —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] —
Uri ng Pagpapasok Surface Mount —
Usable Gates — 5,000 gates
Maximum User I/O — 161
Pin-to-Pin Logic Delay — 10 ns
Maximum Counter Frequency — 227.3 MHz
I/O Logic Level Compatibility — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Programmability — EEPROM, in-system programmable (ISP)
JTAG Interface — IEEE 1532 / JTAG (TDI, TDO, TMS, TCK)
Logic Family — CMOS

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