EPM3512AQC208-10 vs EPM3512AQC208-3 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-10 sa pamamagitan ng Altera at EPM3512AQC208-3 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AQC208-10 EPM3512AQC208-3
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family MAX 3000A MAX 3000A
Usable Gates 10,000 —
Macrocells 512 512
Logic Array Blocks (LABs) 32 16 (32 macrocells each)
User I/Os 208 —
Propagation Delay (tPD) 7.5 ns —
Maximum Frequency (fCNT) 116.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes (IEEE Std. 1532) Yes (IEEE Std. 1532 compliant)
JTAG Boundary Scan Yes (IEEE 1149.1) —
PCI Compliance PCI Local Bus Spec Rev. 2.2 (-10 speed grade) —
Packhaging 208-pin PQFP PQFP-208
Temperature na Operasyon 0C to +70 C (commercial) [DATA_NEEDED: industrial/commercial grade range]
Tindminan RoHS [DATA_NEEDED: RoHS status not in verified data] [DATA_NEEDED: confirm from datasheet]
Device Type — CPLD (Complex Programmable Logic Device)
Maximum User I/O Pins — 172
Speed Grade — -3
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Bank Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (multiVolt)
Boundary-Scan Test — Yes (IEEE Std. 1149.1 / JTAG)
Program/Erase Cycles — 100 minimum [DATA_NEEDED: exact datasheet figure]
Non-Volatile Configuration — Yes (EEPROM-based)
Uri ng Pagpapasok — Surface Mount
Level ng MSL — [DATA_NEEDED: moisture sensitivity level]

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