EPM3512AQC208-10N vs EPM3512AQC208-10S Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-10N sa pamamagitan ng Intel at EPM3512AQC208-10S sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3512AQC208-10N | EPM3512AQC208-10S |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | Up to 10,000 | 1750 |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| User I/Os | 172 | 208 |
| Packhaging | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin FineLine BGA-256 |
| Volte ng Pagbibigay | 3.3 V | — |
| Pin-to-Pin Delay | 4.5 ns (-10 speed grade) | — |
| Maximum Internal Frequency | 227.3 MHz | — |
| Speed Grade | -10 | -10 (tPD1 = 7.5 ns) |
| Process Technology | CMOS EEPROM | EEPROM-based CMOS |
| In-System Programming | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| I/O Standards | MultiVolt (1.8V / 2.5V / 3.3V) | — |
| Temperature na Operasyon | 0 C to 70 C (commercial) | 0C to +70C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status not in verified web data] | [DATA_NEEDED: rohs_status] |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Logic Family | — | CMOS |