EPM3512AQC208-10N vs EPM3512AQC208-7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-10N sa pamamagitan ng Intel at EPM3512AQC208-7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 NrndPagsanggunian na paghahambing
| Parametro | EPM3512AQC208-10N | EPM3512AQC208-7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | Up to 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 172 | 172 |
| Packhaging | 208-pin PQFP (Plastic Quad Flat Pack) | 208-Pin PQFP (FQFP, gull-wing) |
| Volte ng Pagbibigay | 3.3 V | — |
| Pin-to-Pin Delay | 4.5 ns (-10 speed grade) | — |
| Maximum Internal Frequency | 227.3 MHz | — |
| Speed Grade | -10 | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM, 0.30 um |
| In-System Programming | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| I/O Standards | MultiVolt (1.8V / 2.5V / 3.3V) | — |
| Temperature na Operasyon | 0 C to 70 C (commercial) | 0 C to +70 C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status not in verified web data] | Compliant |
| Propagation Delay (tPD) | — | 7.5 ns |
| Counter Frequency (fCNT) | — | 116.3 MHz |
| Logic Elements / LEs | — | N/A (CPLD macrocell architecture) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standards Supported | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Programming | — | In-System Programmable via JTAG (IEEE Std. 1532) |
| Lead-Free | — | Yes |