EPM3512AQC208-7 vs EPM3512AQC208-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-7 sa pamamagitan ng Intel at EPM3512AQC208-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM3512AQC208-7 EPM3512AQC208-7N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Huling Pagbili
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 —
Usable Gates 10,000 —
Propagation Delay (tPD) 7.5 ns 7.5 ns
Counter Frequency (fCNT) 116.3 MHz —
User I/Os 172 172
Logic Elements / LEs N/A (CPLD macrocell architecture) —
Supply Voltage (VCCINT) 3.3 V 3.3 V (3.0 V to 3.6 V)
I/O Standards Supported 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) —
Packhaging 208-Pin PQFP (FQFP, gull-wing) 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing)
Temperature na Operasyon 0 C to +70 C (commercial) 0 °C to +70 °C (commercial)
Programming In-System Programmable via JTAG (IEEE Std. 1532) —
Process Technology CMOS EEPROM, 0.30 um 0.30 µm CMOS EEPROM
Tindminan RoHS Compliant Compliant
Lead-Free Yes —
Logic Capacity — 512 macrocells, 10,000 usable gates
Logic Array Blocks (LABs) — 32
Macrocells per LAB — 16
Maximum Frequency (fCNT) — 116.3 MHz
I/O Bank Count — 4 (MultiVolt)
Supported I/O Standards — 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS
Configuration — Non-volatile EEPROM, in-system programmable (ISP)
JTAG Interface — IEEE 1149.1 BST + IEEE 1532 ISP
Speed Grade — -7

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