EPM3512AQC210-7 vs EPM3512AQC210-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC210-7 sa pamamagitan ng Altera at EPM3512AQC210-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3512AQC210-7 | EPM3512AQC210-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 16 (32 macrocells each) |
| Maximum User I/O Pins | 172 | 172 |
| Dedicated Input Pins | 12 | — |
| Packhaging | PQFP-208 | PQFP-210 |
| Bilang ng Pin | 208 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Operating Voltage (Core) | 3.3 V | — |
| Min Supply Voltage | 3.0 V | — |
| Max Supply Voltage | 3.6 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Pin-to-Pin Delay | 7 ns (speed grade -7) | — |
| Speed Grade | 7 ns | -10 (10 ns tPD) |
| In-System Programmability | Yes (JTAG, IEEE 1149.1) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs_compliance_status] |
| Logic Macrocells | — | 512 |
| Pin-to-Pin Propagation Delay (tPD1, max) | — | 10 ns |
| Maximum Operating Frequency (fCNT) | — | 125 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 3.3 V or 2.5 V |
| Input Voltage Tolerance | — | 5.0 V tolerant |
| Programmable Technology | — | EEPROM (in-system programmable) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |