EPM5016DC-20 vs EPM5032JC25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5016DC-20 sa pamamagitan ng Altera at EPM5032JC25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5016DC-20 | EPM5032JC25 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | — |
| Macrocells | 16 | — |
| Product Terms | 160 | 320 |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | — |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| Maksimum na Taktiko ng Oras | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | — |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | PAL-type macrocells with global Programmable Interconnect Array (PIA) |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Device | — | EPM5032 |
| Logic Elements | — | 32 macrocells |
| Maximum Internal Frequency | — | 62.5 MHz |
| Flip-Flops | — | 32 |
| Bidirectional I/O Pins | — | 16 |
| Total Inputs to Array | — | 24 |
| Bilang ng Outputs | — | 16 |
| Technology | — | CMOS EPROM, UV-erasable (windowed) / OTP |
| Volte ng Pagbibigay | — | 5 V (TTL-level I/O) |
| Packhaging | — | 28-pin PLCC (JC) |
| Uri ng Pagpapasok | — | Surface Mount |