EPM5016DC-20 vs EPM5032JC25 比較
詳細並排比較 EPM5016DC-20 由 Altera 與 EPM5032JC25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5016DC-20 | EPM5032JC25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | — |
| Macrocells | 16 | — |
| Product Terms | 160 | 320 |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | — |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| 最大時脈頻率 | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | — |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | PAL-type macrocells with global Programmable Interconnect Array (PIA) |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Device | — | EPM5032 |
| Logic Elements | — | 32 macrocells |
| Maximum Internal Frequency | — | 62.5 MHz |
| Flip-Flops | — | 32 |
| Bidirectional I/O Pins | — | 16 |
| Total Inputs to Array | — | 24 |
| 輸出數量 | — | 16 |
| Technology | — | CMOS EPROM, UV-erasable (windowed) / OTP |
| 供應電壓 | — | 5 V (TTL-level I/O) |
| 封裝 | — | 28-pin PLCC (JC) |
| 安裝類型 | — | Surface Mount |