EPM5016DI-20 vs EPM5016PC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5016DI-20 sa pamamagitan ng Altera at EPM5016PC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5016DI-20 | EPM5016PC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (UV-erasable CMOS) | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 20 ns | 35 ns |
| Maksimum na Taktiko ng Oras | 62.5 MHz | — |
| Total Inputs | 16 | — |
| Dedicated Inputs | 7 | — |
| Configurable I/O Pins | 8 | — |
| External Clock Inputs | 1 | — |
| Product Terms per Output | 8 | — |
| Output Functions per Macrocell | 8 | — |
| Technology | CMOS EPROM | — |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| Packhaging | 20-pin Ceramic DIP (DI), windowed | PDIP-20 (plastic DIP, through-hole) |
| Speed Grade | -20 (20 ns tPD) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC nominal] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (PDIP with SnPb leads, pre-RoHS era) |
| Usable Gates | — | 200 |
| Logic Array Blocks (LABs) | — | 1 |
| Maximum Frequency (fMAX) | — | 62 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time ns] |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Supply Current (ICC) | — | 50 mA typical |
| Bilang ng Pin | — | 20 |
| Configuration Memory | — | CMOS EEPROM (UV-erasable) |
| Programming Interface | — | Altera 4-pin JTAG-style (MasterBlaster / ByteBlaster) |