EPM5016PC-1 vs EPM5016DC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5016PC-1 sa pamamagitan ng Altera at EPM5016DC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5016PC-1 | EPM5016DC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 |
| Macrocells | 16 | 16 |
| Usable Gates | 200 | — |
| Logic Array Blocks (LABs) | 1 | — |
| Propagation Delay (tPD) | 35 ns | 20 ns |
| Maximum Frequency (fMAX) | 62 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time ns] | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Supply Current (ICC) | 50 mA typical | — |
| Temperature na Operasyon | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Packhaging | PDIP-20 (plastic DIP, through-hole) | — |
| Bilang ng Pin | 20 | — |
| Configuration Memory | CMOS EEPROM (UV-erasable) | — |
| Programming Interface | Altera 4-pin JTAG-style (MasterBlaster / ByteBlaster) | — |
| Tindminan RoHS | Non-compliant (PDIP with SnPb leads, pre-RoHS era) | [DATA_NEEDED: RoHS compliance] |
| Device Type | — | EPLD (UV-Erasable Programmable Logic Device) |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 8 |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| Process Technology | — | CMOS, UV-erasable |
| Architecture | — | PAL-type macrocell with Programmable Interconnect Array (PIA) |
| Package Type | — | 20-pin Ceramic DIP (Cerdip) with UV window |
| Package Suffix Code | — | DC = Ceramic DIP, Commercial |
| Speed Grade | — | -20 = 20 ns tPD |
| Programming Method | — | UV erase + EPROM-style programming via Altera programming hardware |