EPM5032DC-20 vs EPM5032DI-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DC-20 sa pamamagitan ng Intel at EPM5032DI-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032DC-20 EPM5032DI-20
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Family MAX 5000 —
Device Type CPLD (Complex Programmable Logic Device) —
Programmable Technology UV-Erasable / OTP EPROM —
Usable Gates 600 —
Macrocells 32 32
Maximum Frequency (fCNT) 71.4 MHz —
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
Supply Voltage (VCC) 5 V —
Packhaging 20-pin DIP (Windowed Ceramic, 0.3" wide) Ceramic DIP-20 (windowed, UV-erasable)
Uri ng Pagpapasok Through-Hole —
Logic Blocks 4 Logic Array Blocks (LABs) —
I/O Pins [DATA_NEEDED: I/O pin count for DIP-20 variant] —
Temperature na Operasyon [DATA_NEEDED: commercial/industrial/military grade] Industrial (per 'I' suffix)
Tindminan RoHS Compliant (per IC-Components listing) [DATA_NEEDED: RoHS compliance status for ceramic DIP variant]
Lead Free [DATA_NEEDED: confirmed lead-free] —
Manufacturer Altera (now Intel Programmable Solutions Group) —
Programming Method Altera MAX+PLUS II / Quartus (legacy support) —
Family — MAX 5000 (Altera legacy EPLD)
Architecture — CMOS PAL-type EPLD with PIA
Dedicated Inputs — 7
Bidirectional I/O Pins — 16
Product Terms — 320 (maximum)
Flip-Flops — 16 (one per macrocell)
Maksimum na Taktiko ng Oras — 62.5 MHz
Pin-to-Pin Delay — 20 ns (speed grade -20)
Programming — UV-erasable CMOS, JEDEC fuse file
Development Tool — Altera MAX+PLUS II (legacy)
Lead-Free — [DATA_NEEDED: lead-free status]

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