EPM5032DC vs EPM5032DI-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DC sa pamamagitan ng Altera at EPM5032DI-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032DC EPM5032DI-25
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) UV-erasable Programmable Logic Device (PLD)
Macrocells 32 32
Logic Array Blocks (LABs) 1 —
Packhaging DIP-24 (ceramic, windowed) Ceramic DIP, windowed (UV-erasable)
Speed Grade DC (commercial) —
Temperature na Operasyon 0C to +70C 0C to +70C (commercial)
Technology Bipolar EPROM, UV-erasable —
Programmable Logic Elements AND array + fixed OR array per macrocell —
Configuration Memory EPROM (UV-erasable via package window) —
Uri ng Pagpapasok Through-hole (DIP) —
Bilang ng Pin 24 [DATA_NEEDED: exact pin count - 24 or 28]
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: likely non-compliant due to ceramic DIP]
Programming Tool Altera MAX+PLUS II / A+PLUS legacy —
Katayuan ng Lifecycle Obsolete (mature legacy) —
Architecture — PAL-type, CMOS, AND-OR sum-of-products
Product Terms — 320
Logic Gates — [DATA_NEEDED: equivalent gate count]
Dedicated Inputs — 7
Bidirectional I/O Pins — 16
Total Array Inputs — 24
Registered Outputs — 16
Global Clocks — 1
Propagation Delay (tPD) — 25 ns
Maximum Clock Frequency (fMAX) — 62.5 MHz
Volte ng Pagbibigay — 5 V
Process Technology — CMOS
I/O Standard — TTL-compatible
Programmability — UV-erasable, EPROM-based
Development Tool — MAX+PLUS II / A+PLUS
Lifecycle — Not Recommended for New Designs (NRND)

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