EPM5032DC vs EPM5032DI-25 比較
詳細並排比較 EPM5032DC 由 Altera 與 EPM5032DI-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DC | EPM5032DI-25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-erasable Programmable Logic Device (PLD) |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| 封裝 | DIP-24 (ceramic, windowed) | Ceramic DIP, windowed (UV-erasable) |
| Speed Grade | DC (commercial) | — |
| 工作溫度 | 0C to +70C | 0C to +70C (commercial) |
| Technology | Bipolar EPROM, UV-erasable | — |
| Programmable Logic Elements | AND array + fixed OR array per macrocell | — |
| Configuration Memory | EPROM (UV-erasable via package window) | — |
| 安裝類型 | Through-hole (DIP) | — |
| 腳位數 | 24 | [DATA_NEEDED: exact pin count - 24 or 28] |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: likely non-compliant due to ceramic DIP] |
| Programming Tool | Altera MAX+PLUS II / A+PLUS legacy | — |
| 生命週期狀態 | Obsolete (mature legacy) | — |
| Architecture | — | PAL-type, CMOS, AND-OR sum-of-products |
| Product Terms | — | 320 |
| Logic Gates | — | [DATA_NEEDED: equivalent gate count] |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Total Array Inputs | — | 24 |
| Registered Outputs | — | 16 |
| Global Clocks | — | 1 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| 供應電壓 | — | 5 V |
| Process Technology | — | CMOS |
| I/O Standard | — | TTL-compatible |
| Programmability | — | UV-erasable, EPROM-based |
| Development Tool | — | MAX+PLUS II / A+PLUS |
| Lifecycle | — | Not Recommended for New Designs (NRND) |