EPM5032DC vs EPM5032DM883B Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DC sa pamamagitan ng Altera at EPM5032DM883B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032DC | EPM5032DM883B |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 (Classic EPLD) |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Packhaging | DIP-24 (ceramic, windowed) | — |
| Speed Grade | DC (commercial) | — |
| Temperature na Operasyon | 0C to +70C | MILITARY (per /883B screen) |
| Technology | Bipolar EPROM, UV-erasable | UV-erasable EPROM cell |
| Programmable Logic Elements | AND array + fixed OR array per macrocell | — |
| Configuration Memory | EPROM (UV-erasable via package window) | — |
| Uri ng Pagpapasok | Through-hole (DIP) | Through-Hole |
| Bilang ng Pin | 24 | 28 |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: lead-bearing ceramic; likely non-compliant] |
| Programming Tool | Altera MAX+PLUS II / A+PLUS legacy | — |
| Katayuan ng Lifecycle | Obsolete (mature legacy) | — |
| Logic Elements | — | 32 macrocells (MAX architecture) |
| Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns] |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: fCNT in MHz] |
| Supply Voltage (VCC) | — | 5 V (nominal, TTL-compatible I/O) |
| MIL-STD-883 Screening | — | Class B (DM/883B) |
| Package Type | — | WDIP-28 (ceramic DIP with quartz window) |
| Terminal Form | — | Through-Hole |
| Package Shape | — | RECTANGULAR |
| Programming Method | — | Programmer + UV erase |