EPM5032DI-20 vs EPM5032DC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DI-20 sa pamamagitan ng Intel at EPM5032DC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 ObsoletePagsanggunian na paghahambing
| Parametro | EPM5032DI-20 | EPM5032DC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 (Altera legacy EPLD) | MAX 5000 |
| Architecture | CMOS PAL-type EPLD with PIA | — |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Product Terms | 320 (maximum) | — |
| Flip-Flops | 16 (one per macrocell) | — |
| Maksimum na Taktiko ng Oras | 62.5 MHz | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Packhaging | Ceramic DIP-20 (windowed, UV-erasable) | CERDIP-28 (windowed, through-hole) |
| Temperature na Operasyon | Industrial (per 'I' suffix) | 0C to +70C (commercial) |
| Programming | UV-erasable CMOS, JEDEC fuse file | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | unknown |
| Device Type | — | UV-erasable EPLD (PAL-type CMOS) |
| Usable Gates | — | 600 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Toggle Frequency (fMAX) | — | 83.3 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Logic Family | — | CMOS, TTL-compatible I/O |
| Programmable Pins | — | 16 bidirectional I/O + 4 dedicated input = 20 |
| Total Package Pins | — | 28 |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |
| Erasure Method | — | UV light through ceramic quartz window |
| Process Technology | — | CMOS |