EPM5032DI-20 vs EPM5032DC20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DI-20 sa pamamagitan ng Intel at EPM5032DC20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032DI-20 | EPM5032DC20 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 (Altera legacy EPLD) | — |
| Architecture | CMOS PAL-type EPLD with PIA | PAL-type with Programmable Interconnect Array (PIA) |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Product Terms | 320 (maximum) | — |
| Flip-Flops | 16 (one per macrocell) | — |
| Maksimum na Taktiko ng Oras | 62.5 MHz | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Packhaging | Ceramic DIP-20 (windowed, UV-erasable) | 20-pin Ceramic DIP (DC) with UV window |
| Temperature na Operasyon | Industrial (per 'I' suffix) | [DATA_NEEDED: operating temperature range] |
| Programming | UV-erasable CMOS, JEDEC fuse file | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable PLD (CPLD class) |
| Usable Gates | — | 600 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (Fmax) | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| I/O Pins | — | 16 (bidirectional) |
| Total Inputs (max) | — | 24 |
| Output Macrocells | — | 16 |
| Clock Inputs | — | 1 (global) |
| Process Technology | — | CMOS |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |