EPM5032DI25 vs EPM5032DC20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DI25 sa pamamagitan ng Altera at EPM5032DC20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032DI25 | EPM5032DC20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-erasable EPLD (CMOS EPROM-based) | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | — |
| Product Terms | 320 | — |
| Output Macrocells | 16 | 16 |
| Bidirectional I/O Pins | 16 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 24 | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V (4.75 V to 5.25 V) |
| I/O Standard | TTL-compatible | — |
| Packhaging | 24-pin Ceramic DIP (DI) with quartz window | 20-pin Ceramic DIP (DC) with UV window |
| Programming Technology | UV-EPROM (erasable via quartz window) | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable PLD (CPLD class) |
| Usable Gates | — | 600 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (Fmax) | — | 71.4 MHz |
| I/O Pins | — | 16 (bidirectional) |
| Total Inputs (max) | — | 24 |
| Clock Inputs | — | 1 (global) |
| Architecture | — | PAL-type with Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |