EPM5032LC-15 vs EPM5016LC-17 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032LC-15 sa pamamagitan ng Altera at EPM5016LC-17 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032LC-15 | EPM5016LC-17 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 EPLD |
| Architecture | PAL-type AND/OR with PIA | PAL-type with Programmable Interconnect Array (PIA) |
| Usable Gates | 600 | — |
| Macrocells | 32 | 16 |
| Logic Array Blocks (LABs) | 4 | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Maximum Operating Frequency | 83.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS EPROM, 1.0 um process | CMOS, UV-erasable |
| Programmability | UV-Erasable / OTP | — |
| Packhaging | JLCC-28 (windowed ceramic) | Windowed Ceramic DIP (LC) |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| Tindminan RoHS | Non-compliant (contains Pb, ceramic-windowed package) | [DATA_NEEDED: RoHS compliance] |
| Product Terms | — | 160 |
| I/O Pins | — | 8 |
| Total Input Pins | — | 16 |
| Outputs | — | 8 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 17 ns |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |
| Logic Compatibility | — | TTL/CMOS |