EPM5032LC-20 vs EPM5032LC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032LC-20 sa pamamagitan ng Altera at EPM5032LC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032LC-20 | EPM5032LC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | EPLD / CPLD (One-Time Programmable / UV-Erasable) | — |
| Usable Gates | 600 gates | 600 |
| Macrocells | 32 | 32 |
| Logic Blocks (LABs) | 1 | — |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Maximum Frequency | 71.4 MHz | — |
| Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V ±5% | 5 V (4.75 V to 5.25 V) |
| Temperature na Operasyon | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) | 0C to +70C (commercial) |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Inputs | 24 | — |
| Output Functions | 16 | — |
| Product Terms per Output | 16 | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Packhaging | LCC-28 (Plastic Leaded Chip Carrier, J-lead) | JLCC-28 (windowed ceramic) |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (contains Pb, ceramic-windowed package) |
| Level ng MSL | [DATA_NEEDED: MSL] | — |
| Family | — | MAX 5000 EPLD |
| Architecture | — | PAL-type AND/OR with PIA |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Technology | — | CMOS EPROM, 1.0 um process |
| Programmability | — | UV-Erasable / OTP |