EPM5032PC-15 vs EPM5032LC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032PC-15 sa pamamagitan ng Altera at EPM5032LC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032PC-15 | EPM5032LC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | — |
| Macro Cells | 32 | — |
| Usable Gates | 600 | 600 gates |
| Logic Elements / LABs | 1 LAB (4 macrocells per group) | — |
| Propagation Delay (tPD) | 15 ns | 20 ns |
| Maximum Internal Frequency | 76.9 MHz (some sources list 83.3 MHz) | — |
| Operating Voltage (VCC) | 5 V (typ.) | — |
| Technology Node | 0.8 micron CMOS | — |
| Configuration Memory | UV-Erasable EPROM | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Array Inputs | 24 | — |
| Packhaging | 28-pin PDIP (PC suffix = windowed CerDIP) | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| Pin/Package Suffix | PC = Windowed Ceramic DIP | — |
| Speed Grade | 15 (15 ns tPD) | -20 (20 ns pin-to-pin) |
| Temperature na Operasyon | 0C to +70C (commercial) | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) |
| Programming Tool | Altera Logic Programmer + MAX+plus II | — |
| Tindminan RoHS | Non-compliant (CerDIP window, contains Be) | [DATA_NEEDED: RoHS status] |
| Lead-Free | No | — |
| Uri ng Pagpapasok | Through-Hole (DIP) | Surface Mount |
| Product Type | — | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Macrocells | — | 32 |
| Logic Blocks (LABs) | — | 1 |
| Maximum Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V ±5% |
| Total Inputs | — | 24 |
| Output Functions | — | 16 |
| Product Terms per Output | — | 16 |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Level ng MSL | — | [DATA_NEEDED: MSL] |