EPM5064LC vs EPM5128GC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064LC sa pamamagitan ng Altera at EPM5128GC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064LC EPM5128GC-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) UV-erasable CMOS CPLD
Programming Type OTP (One-Time-Programmable, UV-erasable EPROM) —
Macro Cells 64 —
Usable Gates 1.25K 2,500
Logic Array Blocks (LABs) 4 —
Propagation Delay (tPD) 55 ns 16 ns (typical, -1 speed grade)
Total Inputs 36 (7 dedicated + 29 I/O) —
I/O Pins 28 bidirectional + 4 dedicated input —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Temperature na Operasyon 0C to +70C (Commercial) -40C to +85C (industrial)
Packhaging PLCC-44 (LCC-44, J-lead) PGA-96+ (Pin Grid Array, ceramic windowed)
Process Technology CMOS EPROM —
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
Lead Free [DATA_NEEDED: lead-free status] —
Macrocells — 128
Dedicated Inputs — 7
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Maximum Operating Frequency — 62.5 MHz
Technology — CMOS, UV-erasable EPROM
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
Programming Method — UV erase + EPROM program (or device programmer)
Level ng MSL — [DATA_NEEDED: MSL level]

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