EPM5128GC-1 vs EPM5128GC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128GC-1 sa pamamagitan ng Altera at EPM5128GC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128GC-1 EPM5128GC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type UV-erasable CMOS CPLD —
Macrocells 128 128
Usable Gates 2,500 —
Dedicated Inputs 7 —
Maximum User I/O Pins 52 —
Nominal Supply Voltage 5 V —
Supply Voltage Range 4.75 V to 5.25 V —
Maximum Operating Frequency 62.5 MHz 50 MHz
Propagation Delay (tPD) 16 ns (typical, -1 speed grade) Approx. 25 ns (typical, -2 speed grade)
Packhaging PGA-96+ (Pin Grid Array, ceramic windowed) —
Technology CMOS, UV-erasable EPROM —
Temperature na Operasyon -40C to +85C (industrial) 0C to +70C (commercial)
IOL / IOH 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) —
Security Bit Programmable, prevents readback —
Programming Method UV erase + EPROM program (or device programmer) —
Level ng MSL [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] —
Logic Elements / Gates — 2,500 usable gates
Number of Usable Gates — 2,500
Supply Voltage (VCC) — 5 V (nominal)
Package Type — 68-pin PGA (Pin Grid Array)
Package Code (per Partstack) — WPGA
Number of Terminals — 68
Programming Technology — UV-erasable EPROM
Grade (per Partstack) — COMMERCIAL
Terminal Form — PIN/PEG
Configuration Memory — Non-volatile, one-time programmable (erasable via UV)

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