EPM5128JC-2 vs EPM5130JC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128JC-2 sa pamamagitan ng Altera at EPM5130JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5128JC-2 | EPM5130JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | — |
| Macrocells | 128 | 128 |
| Dedicated Inputs | 7 | 19 |
| Propagation Delay (tPD) | 45 ns (max) | 40 ns |
| Maximum Counter Frequency (fCNT) | 50 MHz | — |
| Input Setup Time (tSU) | 7.5 ns | — |
| Output Drive Current (IOH/IOL) | 12 mA DC | — |
| Process Technology | CMOS | CMOS |
| Packhaging | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | 84-pin PLCC (J-lead) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Volte ng Pagbibigay | 5 V (nominal) | — |
| Program/Erase Method | UV (ceramic window) | — |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | — |
| Tindminan RoHS | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS compliance] |
| Logic Family | TTL-compatible I/O | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2,500 gates |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| I/O Pins | — | 80 |
| Programming Technology | — | UV-erasable EPROM (quartz window) |
| External Clock Pins | — | 1 global clock |