EPM5128JC vs EPM5128GC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128JC sa pamamagitan ng Altera at EPM5128GC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128JC EPM5128GC-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Family MAX 5000 —
Device Type EPLD / CPLD UV-erasable CMOS CPLD
Macrocell Count 128 —
Propagation Delay (tPD) 35 ns 16 ns (typical, -1 speed grade)
Logic Elements Programmable AND/OR/XOR array —
Supply Voltage (VCC) 5 V (typical) —
Bilang ng Pins 68 —
Package Type PLCC-68 (JLCC) ceramic, J-leaded —
Dedicated Inputs 8 7
User I/O Pins [DATA_NEEDED: user I/O pin count] —
Configuration Memory UV-erasable EPROM (windowed package) —
Programming Interface Altera MAX+PLUS II / A+PLUS / legacy programmer —
Temperature na Operasyon Commercial 0C to +70C -40C to +85C (industrial)
Uri ng Pagpapasok Surface Mount (PLCC socket or solder) —
Boundary Scan JTAG IEEE 1149.1 (family feature) —
Process Technology CMOS EPROM —
Tindminan RoHS [DATA_NEEDED: RoHS status - legacy part] [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
Lead-Free [DATA_NEEDED: lead-free status] —
Family — MAX 5000
Macrocells — 128
Usable Gates — 2,500
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Maximum Operating Frequency — 62.5 MHz
Packhaging — PGA-96+ (Pin Grid Array, ceramic windowed)
Technology — CMOS, UV-erasable EPROM
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
Programming Method — UV erase + EPROM program (or device programmer)
Level ng MSL — [DATA_NEEDED: MSL level]

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