EPM5128LC-1 vs EPM5128JC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128LC-1 sa pamamagitan ng Altera at EPM5128JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5128LC-1 | EPM5128JC |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Logic Elements / Macrocells | 128 macrocells | — |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | — |
| Dedicated Inputs | 7 | 8 |
| Bidirectional I/O Pins | 52 | — |
| Total User I/O | 60 (max) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Supply Voltage (VCC) | 5 V (±10%) | 5 V (typical) |
| Process Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Programmability | UV-erasable / OTP (windowed package) | — |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | PLCC-68 (JLCC) ceramic, J-leaded |
| Temperature na Operasyon | 0C to +70C (commercial) | Commercial 0C to +70C |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Uri ng Pagpapasok | Surface Mount (J-lead PLCC socket compatible) | Surface Mount (PLCC socket or solder) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - legacy part] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Product Family | — | MAX 5000 |
| Device Type | — | EPLD / CPLD |
| Macrocell Count | — | 128 |
| Propagation Delay (tPD) | — | 35 ns |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Bilang ng Pins | — | 68 |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Configuration Memory | — | UV-erasable EPROM (windowed package) |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |