EPM5128LC-1 vs EPM5130GI Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128LC-1 sa pamamagitan ng Altera at EPM5130GI sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5128LC-1 | EPM5130GI |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Logic Elements / Macrocells | 128 macrocells | — |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | — |
| Dedicated Inputs | 7 | 19 |
| Bidirectional I/O Pins | 52 | — |
| Total User I/O | 60 (max) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Supply Voltage (VCC) | 5 V (±10%) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS |
| Programmability | UV-erasable / OTP (windowed package) | — |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | -40C to +85C (industrial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Uri ng Pagpapasok | Surface Mount (J-lead PLCC socket compatible) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | MAX 5000 |
| Architecture | — | EPLD (Erasable Programmable Logic Device), UV-erasable |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Total Inputs | — | 68 |
| I/O Pins | — | 48 |
| Propagation Delay (tPD) | — | 55 ns |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| External Clock Pins | — | 1 |
| Volte ng Pagbibigay | — | 5 V |
| Packhaging | — | Ceramic Pin Grid Array (PGA), windowed |
| Programming Method | — | UV erasure + EPROM programming |