EPM5130GI vs EPM5192GI Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130GI sa pamamagitan ng Altera at EPM5192GI sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130GI | EPM5192GI |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Architecture | EPLD (Erasable Programmable Logic Device), UV-erasable | — |
| Macrocells | 128 | 192 |
| Logic Array Blocks (LABs) | 8 | 16 (12 macrocells per LAB) |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Dedicated Inputs | 19 | 7 |
| Total Inputs | 68 | 72 |
| I/O Pins | 48 | — |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | — |
| External Clock Pins | 1 | — |
| Process Technology | CMOS | — |
| Volte ng Pagbibigay | 5 V | — |
| Packhaging | Ceramic Pin Grid Array (PGA), windowed | — |
| Temperature na Operasyon | -40C to +85C (industrial) | -40 C to +85 C (Industrial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not confirmed in verified web data] |
| Programming Method | UV erasure + EPROM programming | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Technology | — | CMOS EPROM (UV-erasable / OTP) |
| User I/O Pins | — | 64 |
| Maximum Internal Frequency (fCNT) | — | 33.3 MHz |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Package Type | — | 84-pin PGA (Pin Grid Array), ceramic with quartz window |
| Programmable | — | UV-erasable (windowed) and OTP variants |
| Uri ng Pagpapasok | — | Through-hole (PGA) |