EPM5130JI vs EPM5128JI-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130JI sa pamamagitan ng Altera at EPM5128JI-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130JI | EPM5128JI-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 5000 | — |
| Device Type | UV-Erasable EPLD (CMOS EPROM) | UV-Erasable Programmable Logic Device (PLD) |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | — |
| Maksimum na Taktiko ng Oras | 33.3 MHz | 50 MHz |
| Propagation Delay (tPD) | 55 ns | 45 ns |
| External Clock Inputs | 1 (shared input/clock) | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Process Technology | 0.75 micron CMOS EPROM | CMOS EPROM |
| Volte ng Pagbibigay | 5 V (typical) | — |
| Input Logic Standard | TTL-compatible | — |
| Package Type | Ceramic J-Leaded Chip Carrier (JLCC) with UV window | Ceramic J-Lead (JI) with UV window |
| Temperature na Operasyon | Commercial (0C to +70C) | -40 C to +85 C (industrial) |
| Program/Erase Method | UV erasure through quartz window | — |
| Tindminan RoHS | Non-compliant (contains Pb in ceramic package) | unknown |
| Lifecycle | Obsolete - EOL by Altera/Intel | — |
| Series | — | MAX 5000 |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 52 |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Programmability | — | UV-erase, parallel programmer |
| Architecture | — | LAB-based macrocell, segmented interconnect |
| Speed Grade | — | -2 (industrial-speed) |
| Lead-Free | — | unknown |