EPM5130JI vs EPM5128JI-2 比較
詳細並排比較 EPM5130JI 由 Altera 與 EPM5128JI-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5130JI | EPM5128JI-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 | — |
| Device Type | UV-Erasable EPLD (CMOS EPROM) | UV-Erasable Programmable Logic Device (PLD) |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | — |
| 最大時脈頻率 | 33.3 MHz | 50 MHz |
| Propagation Delay (tPD) | 55 ns | 45 ns |
| External Clock Inputs | 1 (shared input/clock) | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Process Technology | 0.75 micron CMOS EPROM | CMOS EPROM |
| 供應電壓 | 5 V (typical) | — |
| Input Logic Standard | TTL-compatible | — |
| Package Type | Ceramic J-Leaded Chip Carrier (JLCC) with UV window | Ceramic J-Lead (JI) with UV window |
| 工作溫度 | Commercial (0C to +70C) | -40 C to +85 C (industrial) |
| Program/Erase Method | UV erasure through quartz window | — |
| RoHS 狀態 | Non-compliant (contains Pb in ceramic package) | unknown |
| Lifecycle | Obsolete - EOL by Altera/Intel | — |
| Series | — | MAX 5000 |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 52 |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Programmability | — | UV-erase, parallel programmer |
| Architecture | — | LAB-based macrocell, segmented interconnect |
| Speed Grade | — | -2 (industrial-speed) |
| Lead-Free | — | unknown |