EPM5130QC-1 vs EPM5130LC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130QC-1 sa pamamagitan ng Altera at EPM5130LC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130QC-1 | EPM5130LC |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 (EPM51xx) |
| Product Type | UV-Erasable / OTP Complex PLD (CPLD) | — |
| Logic Cells / Macrocells | 128 macrocells | — |
| Usable Gates (marketing) | 5130 gates | — |
| Speed Grade | -1 | — |
| Packhaging | PQFP-100 (windowed ceramic) | JLCC-68 (J-Lead Ceramic Chip Carrier) |
| Terminal Pitch | 0.635 mm | — |
| Process Technology | CMOS | CMOS (0.7 um EPROM) |
| Configuration Memory | UV-Erasable EPROM | — |
| Volte ng Pagbibigay | 5 V (single) | — |
| Temperature na Operasyon | Commercial (0 C to +70 C) | [DATA_NEEDED: commercial/industrial/military grade] |
| Programmable Polarity | Yes (per macrocell) | — |
| Boundary Scan / JTAG | Per MAX 5000 family | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Non-compliant (ceramic JLCC, contains lead) |
| Series | — | MAX 5000 |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| User I/O Pins | — | 48 |
| Total Inputs (Dedicated + I/O) | — | 68 |
| Dedicated Inputs | — | 19 |
| Propagation Delay (tPD) | — | 55 ns |
| Maximum Internal Clock Frequency | — | 50 MHz |
| Global Clock Inputs | — | 1 |
| Configuration Technology | — | UV-Erasable / OTP EPROM |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| I/O Standard | — | TTL-compatible |